Exemplary embodiments of the present invention relate generally to an integrated circuit and more particularly to a data output driver and an integrated circuit including the same.
Ongoing trends for the integrated circuit (IC) include a high degree of integration, low power consumption, and a fast operating speed. In addition, the data output circuit of the integrated circuit (IC) requires data reliability.
FIG. 1A shows a memory device including a data output driver circuit.
Referring to FIG. 1A, the memory device 100 includes an output pre-driver 120 coupled to a memory chip 110, including memory cells for storing data, and an output driver 130.
The memory chip 110 includes circuits for storing data in the memory cells and reading stored data from the memory cells. Data Dout outputted from the memory chip 110 is pulled up (PU) or pulled down (PD) by the output pre-driver 120 and then transferred to the output driver 130.
The output driver 130 outputs the pull-up signal PU and the pull-down signal PD of the output pre-driver 120 to a data line DQ.
FIG. 1B shows the output pre-driver 120 and the output driver 130 of FIG. 1A.
Referring to FIG. 1B, the output pre-driver 120 includes first and second PMOS transistors P1 and P2 and first and second NMOS transistors N1 and N2. Furthermore, the output driver 130 includes a third PMOS transistor P3 and a third NMOS transistor N3.
The first PMOS transistor P1 and the first NMOS transistor N1 correspond to a pull-up unit for pulling up the data Dout, received from the memory chip 110, to a power supply voltage level when the data Dout is in a logic low and outputs the pulled-up data as the pull-up signal PU. The second PMOS transistor P2 and the second NMOS transistor N2 correspond to a pull-down unit for pulling down the data Dout, received from the memory chip 110, to a ground voltage level when the data Dout is in a logic high and outputs the pulled-up data as the pull-down signal PU. The output driver 130 outputs data of the power supply voltage level in response to the pull-up signal PU of the ground voltage level and outputs data of the ground voltage level in response to the pull-down signal PD of the power supply voltage level.
The output pre-driver 120 and the output driver 130 pull up the voltage level of data to the power supply voltage level or pull down the voltage level of data to the ground voltage level. If a power supply voltage of 3.3 V is supplied to the output driver 130, the voltage level of the data pulled up at the output driver 130 becomes 3.3 V.
If a plurality of memory chips 110 is included in the memory device 100, each memory chip 110 is operated by the same power supply voltage, and thus the output pre-driver 120 and the output driver 130 of each memory chip 110 is operated by the same power supply voltage.
FIG. 2 shows data outputted from a plurality of memory chips (e.g., memory chips of a multi-chip package) and operating voltages of the memory chips.
As shown in FIG. 2, in an ideal case, a tilt that a voltage level of data shifts from a low level to a high level or from a high level to a low level is 90 degrees irrespective of an operating voltage or the number of memory chips. The tilt, in other word, a slew rate may vary according to the number of memory chips which are allocated to the output driver. In addition, a strength of the output driver 130 may vary according to an operating voltage and the number of memory chips which are allocated to the output driver.
Therefore, data outputted through the output pre-driver 120 and the output driver 130 of FIG. 1A may have a low reliability.